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exar corporation 48720 kato road, fremont ca, 94538 ? (510) 668-7000 ? fax (510) 668-7017 ? www.exar.com ? ? ? ? preliminary XR16L651 2.5v, 3.3v and 5v low power uart with 32-byte fifo january 2001 rev. p1.0.0 general description the XR16L651 1 (651) is a 2.5v, 3.3v and 5v univer- sal asynchronous receiver and transmitter (uart) with 5v tolerant inputs. this new device supports intel and motorola data bus interface and is software com- patible to industry standard 16c450, 16c550, st16c580 and st16c650a uarts. the 651 has 32 bytes of tx and rx fifos and is ca- pable of operating up to serial data rate of 2 mbps at 3.3v supply voltage. the internal registers include the 16c550 register set plus exars enhanced registers for additonal features to support todays highly de- manding data communication needs. the enhanced features include automatic hardware and software flow control, selectable tx and rx trigger levels, and wireless infrared (irda) encoder/decoder. the device provides a new capability to give user the ability to program the wireless infrared encoder out- put pulse width, hence, reduces the power consump- tion of the handheld unit. the XR16L651 device comes in in a small 7x7x1mm 48-pin tqfp package with commercial and industrial temperature ranges. n ote : covered by us patents #5,649,122 and #5,949,787 n ote : underline features are exclusive to XR16L651. features ? 2.5v, 3.3v and 5v operation w/ 5v tolerant inputs 2 ? st16c450/550/580/650a software compatible ? intel, motorola 2 or pc mode 8-bit bus interface ? up to 1mbps data rate at 3.3v operation ? 32-byte transmit and receive fifos ? automatic hardware (rts/cts) flow control ? hardware flow control hysteresis ? automatic software (xon/xoff) flow control ? infrared (irda) encoder/decoder enable inpu t 2 ? programmable infrared encoder pulse witdh ? sleep mode with wake-up indicator ? 48-pin tqfp package (7x7x1mm) ? commercial and industrial temperature grades applications ? battery operated electronics ? internet appliances ? handheld terminal ? personal digital assistants ? cellular phones dataport ? wireless infrared data communications systems f igure 1. b lock d iagram xtal1/clk xtal2 crystal osc/buffer dtr#, dsr#, rts#, cts#, cd#, ri# intel, motorola or pc data bus interface 32 byte tx fifo baud rate generator infrared encoder and pulse width control transmitter uart configuration regs ior ior# 32 byte rx fifo infrared decoder receiver with auto software flow control modem control signals tx rx cts flow control rts flow control brg prescaler cs1 cs0 ddis# int txrdy# rdrdy# a2:a0 d7:d0 iow cs2# im# pcmode# s1 s2 s3 irqa irqb irqc iow#/r/w# reset pc mode: com 1 to 4 decode logic enir
XR16L651 ? ? ? ? 2.5v, 3.3v and 5v low power uart with 32-byte fifo rev. p1.0.0 preliminary 2 f igure 2. i ntel , m otorola and pc mode p in o ut . 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 37 38 39 40 41 42 43 44 45 46 47 48 XR16L651 48-tqfp in intel b us m ode n.c. d5 d6 d7 rlck a4 rx tx cs0 cs1 cs2# baudout as# txrdy# ddis# s1 ior ior# gnd iow iow # xtal2 xtal1 enir vcc reset op1# dtr# rts# op2# int rxrdy# a0 a1 a2 n.c gnd a9 cts# dsr# cd# ri# vcc d0 d1 d2 d3 d4 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 37 38 39 40 41 42 43 44 45 46 47 48 XR16L651 48-tqfp in m otorola bus m ode n.c. d5 d6 d7 rlck a4 rx tx cs0 cs1 cs2# baudout as# txrdy# ddis# s1 gnd gnd gnd gnd r/w # xtal2 xtal1 enir vcc reset# op1# dtr# rts# op2# int# rxrdy# a0 a1 a2 n.c vcc a9 cts# dsr# cd# ri# vcc d0 d1 d2 d3 d4 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 37 38 39 40 41 42 43 44 45 46 47 48 XR16L651 48-tqfp in p c m ode n.c. d5 d6 d7 s2 a4 rx tx a5 a6 a7 lpt1# aen# irq c lpt2# s1 a3 ior# gnd a8 iow # xtal2 xtal1 enir gnd reset op1# dtr# rts# s3 irqa irqb a0 a1 a2 n.c gnd a9 cts# dsr# cd# ri# vcc d0 d1 d2 d3 d4 intel bus m ode w ith im # tied to g n d and pcmode# tied to vcc motorola bus mode with im # tied to v c c and pcmode# tied to vcc pc mode with im# and pcmode# tied to gnd im # : pin 37 pcmode# : pin 36 ordering information p art n umber p ackage o perating t emperature r angr XR16L651cm 48-tqfp 0c to +70c XR16L651im 48-tqfp -40c to +85c
? ? ? ? XR16L651 2.5v, 3.3 and 5v low power uart with 32-byte fifo preliminary rev. p1.0.0 3 pin descriptions n ote : pin type: i=input, o=output, io= input/output, od=output open drain. n ame p in #t ype d escription 16 (intel) or 68 (motorola) mode data bus interface. the pcmode# pin is connected to vcc. a2-a0 26,27,28 i address data lines [2:0]. a0:a2 selects internal uarts configuration registers. d7:d0 4,3,2,48-44 io data bus lines [7:0] (bidirectional). ior# 19 i input/output read (active low). when im# pin is at logic 0, it selects intel bus interface and this input is read strobe (active low). the falling edge instigates an internal read cycle and retrieves the data byte from an internal register pointed by the address lines [a2:a0], places it on the data bus to allow the host processor to read it on the leading edge. when im# pin is at logic 1, it selects motorola bus interface and the ior# input is not used and it should be connected to gnd to minimize supply curent. its function is the same as ior, except it is active low. either an active ior# or ior is required to transfer data from 651 to cpu during a read operation. ior 20 input/output read (active high). same as ior# but active high. when im# pin is at logic 1 for motorola bus mode, this pin is not used and should be con- nected to gnd to minimize supply curent. iow# (r/w#) 16 i when im# pin is at logic 0, it selects intel bus interface and this input becomes write strobe (active low). the falling edge instigates the internal write cycle and the trailing edge transfers the data byte on the data bus to an internal register pointed by the address lines [a2:a0]. its function is the same as iow, except it is active low. either an active iow# or iow is required to transfer data from 651 to the intel type cpu during a write operation. when im# pin is at logic 1, it selects motorola bus interface and this input becomes r/w# signal for read (logic 1) and write (logic 0). iow 17 input/output write. same as iow# but active high. when im# pin is at logic 1 for motorola bus mode, this pin must be connected to gnd to allow iow# input to function correctly. cs0 9 i chip select 0 input (active high). this input selects the XR16L651 device. if cs1 or cs2# is used as the chip select then this pin must be connected to vcc. cs1 10 chip select 1 input (active high). this input selects the XR16L651 device. if cs0 or cs2# is used as the chip select then this pin must be connected to vcc. cs2# 11 chip select 2 input (active low). this input selects the XR16L651 device. if cs0 or cs1 is used as the chip select then this pin must be connected to gnd. int (int#) 30 o interrupt output. this output becomes active whenever the transmitter, receiver, line and/or modem status register has an active condition. see inter- rupt section for more detail. when im# pin is at logic 0 (intel bus mode), this interrupt output may be set to normal active high or active high open source to provide wire-or capability by connecting a 1k to 10k ohms resistor between this pin and ground. when im# pin is at logic 1 (motorola bus mode), this interrupt output becomes an open drain, active low output. it requires an external pull-up resistor of 1k-10k ohms to operate properly. the output may be wire-ored with other devices in the system to form a single interrupt request to the host processor and have the software driver poll all devices to determine the interrupting condition(s).
XR16L651 ? ? ? ? 2.5v, 3.3v and 5v low power uart with 32-byte fifo rev. p1.0.0 preliminary 4 as# 24 i address strobe input (active low). in the intel bus mode, the leading-edge transition of as# latches the chip selects (cs0, cs1, cs2#) and the address lines a0, a1 and a2. this input is used when the address lines and chip select inputs are not stable for the duration of a read or write operation, i.e.,for a processor that needs to de-multiplex the address and data lines. if not required, this input can be permanently tied to gnd. this input is not used in the motorola mode. pc mode interface signals. connect pcmode# pin to gnd and im# pin to gnd to select pc mode. a3, a4, a5, a6, a7, a8, a9 20, 6, 9, 10,11,17,38 i in the pc mode, these are the addtional address lines from the host address bus. they are inputs to the on-board chip select decode function for com 1-4 and lpt ports. see table 1 for details. the pins a4 and a9 have internal 100k w pull-up resistors. aen# 24 i address enable input (active low). when aen# transition to logic 0, it decodes and validates com 1-4 ports address per s1, s2 and s3 inputs. s1, s2, s3 21,5,31 i select 1 to 3. these are the standard pc com 1-4 ports and irq selection inputs. see table 1 and table 2 for details. the s1 pin has an internal 100k w pull-up resistor. irqa, irqb, irqc 30,29,23 o interrupt request a, b and c outputs (active high, tri-state). these are the interrupt outputs associated with com 1-4 to be connected to the host data bus. see interrupt section for details. the interrupt requests a, b or c func- tions as irqx to the pc bus. irqx is enabled by setting mcr bit-3 to logic 1 and the desired interrupt(s) in the interrupt enable register (ier). lpt1# 12 o line printer port-1 decode logic output (active low). this pin functions as the pc standard lpt-1 printer port address decode logic output, see table 1. the baud rate generator clock output, baudout#, is internally connected to the rclk input in the pc mode. lpt2# 22 o line printer port-2 decode logic output (active low) - this pin functions as the pc standard lpt-2 printer port address decode logic output, see table 1. modem or serial i/o interface tx 8 o transmit data or wireless infrared transmit data. this output is active low in normal standard serial interface operation (rs-232, rs-422 or rs-485) and active high in the infrared mode. infrared mode can be enabled by connecting pin enir to vcc or through software settling after power up. rx 7 i receive data or wireless infrared receive data. normal received data input idles at logic 1 condition and logic 0 in the infrared mode. the wireless infra- red pulses are applied to the decoder. this input must be connected to its idle logic state in either normal, logic 1, or infrared mode, logic 0, else the receiver may report receive break and/or error condition(s). rts# 32 o request to send or general purpose output (active low). this port may be used for one of two functions: 1) automatic hardware flow control, see efr bit-6, mcr bits-1 & 2, fctr bits 0-3 and ier bit-6. 2) rs485 half-duplex direction control, see fctr bit-5, mcr bit-2 and msr bits 4-7. rts# output must be asserted before auto rts flow control can start. n ame p in #t ype d escription
? ? ? ? XR16L651 2.5v, 3.3 and 5v low power uart with 32-byte fifo preliminary rev. p1.0.0 5 cts# 39 i clear to send or general purpose input (active low). if used for automatic hardware flow control, data transmission will be stopped when this pin is de- asserted and will resume when this pin is asserted again. see efr bit-7, mcr bit-2 and ier bit-7. dtr# 33 o data terminal ready or general purpose output (active low). dsr# 40 i data set ready input or general purpose input (active low). cd# 41 i carrier detect input or general purpose input (active low). ri# 42 i ring indicator input or general purpose input (active low). ancillary signals xtal1 14 i crystal or external clock input. xtal2 15 o crystal or buffered clock output. rclk 5 i this input is used as external 16x clock input to the receiver section. connect the -baudout pin to this input externally. baudout# 12 o baud rate generator output (active low). this pin provides the 16x clock of the selected data rate from the baud rate generator. the rclk pin must be connected externally to baudout# when the receiver is operating at the same data rate. when the pc mode is selected, the baud rate generator clock output is inter- nally connected to the rclk input. this pin then functions as the lpt-1 printer port decode logic output, see table 2. pcmode# 36 i pc mode select (active low). when this input is at logic 0, it enables the on- board chip select decode function according to pc isa bus com[4:1] and irq[4,3] port definitions. see table 2 for details. this pin has an internal 100k w pull-up resistor. ddis# 22 o drive disable output. this pin goes to a logic 0 whenever the host cpu is reading data from the 651. it can control the direction of a data bus trans- ceiver between the cpu and 651 or other logic functions. enir 13 i enable infrared mode (active high). this pin can be used to start up the uart in wireless infrared mode upon power up or a reset. the tx output would idle at logic 0 instead of normal logic 1. the software infrared enable bit (mcr bit- 6) will have full enable/disable control after the power up. reset (reset#) 35 i reset input. when it is asserted, the uart configuration registers are reset to default values, see table 13. when im# pin is at a logic 0, intel bus mode, reset input is active high. when im# pin is at a logic 1, motorola bus mode, reset input is active low. im# 37 i intel or motorola data bus interface select. a logic 0 selects intel bus interface and a logic 1 selects motorola interface. this input affects the functionality of ior#, iow#, cs# and int pins. op1# 34 o output port 1. general purpose output. op2# 331 o output port 2. general purpose output. vcc 43 2.5v, 3.3v or 5v. gnd 18 power supply common ground. nc 1,25 no connect. conenct to vcc or gnd to minimize noise. n ame p in #t ype d escription
XR16L651 ? ? ? ? 2.5v, 3.3v and 5v low power uart with 32-byte fifo rev. p1.0.0 preliminary 6 product description the XR16L651 (651) is industry first multi-voltage uart that can operate at 2.5, 3.3 or 5v power sup- plies. its inputs are 5v tolerant to facilitate intercon- nection to transceiver devices of rs-232, rs-422 or rs-485. the 651 is software compatible to the indus- try standad 16c550 with additional enhanced fea- tures. the 651 provides serial asynchronous receive data synchronization, parallel-to-serial and serial-to-paral- lel data conversions for both the transmitter and re- ceiver sections. these functions are necessary for converting the serial data stream into parallel data that is required with digital data systems. synchroni- zation for the serial data stream is accomplished by adding start and stops bits to the transmit data to form a data character (character orientated protocol). data integrity is ensured by attaching a parity bit to the data character. the parity bit is checked by the re- ceiver for any transmission bit errors. the electronic circuitry to provide all these functions is fairly complex especially when manufactured on a single integrated silicon chip. the XR16L651 represents such an inte- gration with greatly enhanced features. the 651 is fabricated with an advanced cmos process. the 651 supports standard 8-bit intel, motorola or pc bus interfaces through 2 input selection pins. the in- tel bus uses separate input/output read and write sig- nals for all bus transactions while the motorola bus uses a read/write signal and chip select to conduct the same transactions. the pc bus mode associates with the pc isa bus and follow the industry standard pc definitions for com 1-4 serial port addresses. the 651 includes on-board chip select decode logic and selection for the proper interrupt request. this elimi- nates the need for an external logic array device. the 651 has 32-byte each of transmit and receive fifos, automatic rts/cts hardware flow control with hysteresis, automatic xon/xoff and special char- acter software flow control, programmable transmit and receive fifo trigger levels, wireless infrared en- coder and decoder (irda ver 1.0), programmable baud rate generator with a prescaler of divide by 1 or 4, and data rate up to 1.0 mbps at 16x sampling clock rate. the 651 is an upward solution that provides 32 bytes of transmit and receive fifo memory, instead of 16 bytes provided in the 16c550, or none in the 16c450. the 651 is designed to work with high speed commu- nication devices, that require fast data processing time. increased performance is realized in the 651 by the larger transmit and receive fifos. this allows the external processor to handle more networking tasks within a given time. for example, the standard st16c550 with a 16 byte fifo, unloads 16 bytes of receive data in 1.53 ms (this example uses a charac- ter length of 11 bits, including start/stop bits at 115.2kbps). this means the external cpu will have to service the receive fifo at 1.53 ms intervals. how- ever with the 32 byte fifo in the 651, the data buffer will not require unloading/loading for 3.05 ms. this in- creases the service interval giving the external cpu additional time for other applications and reducing the overall uart interrupt servicing time. in addition, the 4 selectable levels of fifo trigger interrupt and auto- matic hardware/software flow control is uniquely pro- vided for maximum data throughput performance es- pecially when operating in a multi-channel environ- ment. the combination of the above greatly reduces the bandwidth requirement of the external controlling cpu, increases performance, and reduces power consumption. the rich feature set of the 651 is available through in- ternal registers. automatic hardware/software flow control, selectable transmit and receive fifo trigger levels, selectable tx and rx baud rates, infrared en- coder/decoder interface, modem interface controls, and a sleep mode are all standard features. in the pc mode, two tri-state interrupt lines (irqb and irqc) and one selectable open source interrupt output (irqa) are available. the open source interrupt scheme allows multiple interrupts to be combined in a wire-or operation, thus reducing the number of in- terrupt lines in larger systems. following a power on reset or an external reset, the 651 is software com- patible with previous generation of uarts, 16c450, 16c550 and st16c650a.
? ? ? ? XR16L651 2.5v, 3.3 and 5v low power uart with 32-byte fifo preliminary rev. p1.0.0 7 functional descriptions 1.0 host data bus interface the host interface is a 8 data bit wide with 3 address lines and control signals to execute bus read and write transactions. the 651 supports 3 type of host in- terfaces: intel, morotola and pc mode. the intel and motorola interfaces provide support for their respec- tive microcontroller or processor. this facilitates the hardware design and interconnections. the intel bus interface is selected by connecting im# to logic 0 and pcmode# to logic 1. the intel bus interconnections are shown in figure 3. the motorola bus is selected with the im# input connected to logic 0 and pc- mode# input ties to logic 1. the motorola bus inter- connections are shown in figure 4. the special pc mode is selected when im# and pcmode# are con- nected to logic 0. the pc mode interconnections are shown in figure 5. t f igure 3. XR16L651 i ntel b us i nterconnections d0 d1 d2 d3 d4 d5 d6 d7 a0 a1 a2 io r* io w * reset d0 d1 d2 d3 d4 d5 d6 d7 io r# io w # a0 a1 a2 cs2# reset vcc cs0 cs1 as# io r io w int int rclk baudout# pcmode# im # vcc gnd cs# op2# op1# dsr# cts# rts# dtr# rx tx ri# cd#
XR16L651 ? ? ? ? 2.5v, 3.3v and 5v low power uart with 32-byte fifo rev. p1.0.0 preliminary 8 . . f igure 4. XR16L651 m otorola b us i nterconnections . d0 d1 d2 d3 d4 d5 d6 d7 a0 a1 a2 cs# r/w # reset# d0 d1 d2 d3 d4 d5 d6 d7 io r# io w # a0 a1 a2 cs2# reset# vcc cs0 cs1 as# io r io w int# int# rclk baudout# pcmode# im # vcc gnd op2# op1# dsr# cts# rts# dtr# rx tx ri# cd# vcc f igure 5. XR16L651 pc m ode i nterconnections d0 d1 d2 d3 d4 d5 d6 d7 a0 a1 a2 a3 a4 a5 a6 a7 a14 a15 aen# io w # io r# reset d0 d1 d2 d3 d4 d5 d6 d7 io w # a0 a1 a2 reset vcc cs0 cs1 as# io r io w irq n irq a pcmode# im # vcc gnd io r# irq b irq c irq 4 irq 3 a3 a4 a5 a6 a7 a8 a9 aen* op1# ri# cd# dsr# cts# rx tx rts# dtr# s1 s2 s3 vcc gnd gnd
? ? ? ? XR16L651 2.5v, 3.3 and 5v low power uart with 32-byte fifo preliminary rev. p1.0.0 9 1.1 pc mode the pc mode interface includes an on-chip address decoder and interrupt selection function for the stan- dard pc com 1-4 ports addresses. the selection is made through three input signals: s1, s2 and s3. the selection summary is shown in table 1. although the on-chip address decoder was designed for pc applications ranging from 0x278 to 0x3ff, it can fit in- to an embedded applications by offsetting the ad- dress lines to the 651. an example is shown in figure 6 where the uart is operating from 0xc0f8 to 0xc0ff address space. operating in the pc mode eliminates external address decode components. t able 1: pc m ode i nterface o n - chip a ddress d ecoder and i nterrupt s election . pcmode# input s3, s2, s1 i nputs a3-a9 a ddress l ines to o n - chip d ecoder com/lpt p ort s election irq o utput s election 0 0 0 0 0x3f8 - 0x3ff com-1 irqb (for pcs irq4) 0 0 0 1 0x2f8 - 0x2ff com-2 irqc (for pcs irq3) 0 0 1 0 0x3e8 - 0x3ef com-3 irqb (for pcs irq4) 0 0 0 0 0x3f8 - 0x3ff com-4 irqb (for pcs irq4) 0 1 0 0 0x2f8 - 0x2ff com-1 irqa (for pcs irqn 0 1 0 1 0x3e8 - 0x3ef com-2 irqa (for pcs irqn) 0 1 1 0 0x2e8 - 0x2ef com-3 irqa (for pcs irqn) 0 1 1 1 0x3f8 - 0x3ff com-4 irqa (for pcs irqn) 0 - - - 0x278 - 0x27f lpt-2 n/a 0 - - - 0x378 - 0x37f lpt-1 n/a f igure 6. pc m ode i nterface in an e mbedded a pplication . d0 d1 d2 d3 d4 d5 d6 d7 a0 a1 a2 a3 a4 a5 a6 a7 a14 a15 aen# io w # io r# reset d0 d1 d2 d3 d4 d5 d6 d7 io w # a0 a1 a2 reset vcc cs0 cs1 as# io r io w int irq a pcmode# im # vcc gnd io r# irq b irq c a3 a4 a5 a6 a7 a8 a9 aen* op1# ri# cd# dsr# cts# rx tx rts# dtr# s1 s2 s3 vcc gnd gnd embedded application set to operate at address 0xc0f8 to 0xc0ff
XR16L651 ? ? ? ? 2.5v, 3.3v and 5v low power uart with 32-byte fifo rev. p1.0.0 preliminary 10 2.0 interrupt the output function of interrupt, int, output changes according to the operating bus type and various fac- tors. table 2 sumarizes its behaviour in intel, motoro- la and pc mode of operation. multiple interrupts can be wire-ored. this is accomplished by setting mcr bit-5 to a logic 1 and connecting a 1k to 10k ohms re- sistor between this pin and ground to provide an ac- ceptable logic 0 level. t able 2: i nterrupt o utput (int, int# and irqa) f unctions im# i nput (i ntel / m otorola ) pcmode# i nput s3 i nput mcr bit -5 (int type select ) mcr bit -3 (irq n enable ) i nterrupt o utput (int, int# or irqa) intel bus mode 1 1 dont care 0 dont care int is logic 0 for inactive interrupt. int is logic 1 for active interrupt (active high) 1 1 dont care 1 dont care int is tri-state for inactive interrupt int is logic 1 for active interupt (open source). requires a 1k-10k ohms resistor to gnd. motorola bus mode 0 x dont care 0 dont care int# is tri-state for inactive interrupt. int# is logic 0 for active interrupt (actie low, open drain). requires a 1k-10k ohms resistor to vcc. 0 x dont care 1 dont care int# is tri-state. pc mode 1 0 0 dont care dont care irqa is tri-state. either irqb or irqc is used, see table 1. 1 0 1 dont care 0 irqa is tri-state. 1 0101irqa is logic 0 for iactive interrupt. irqa is logic 1 for active interrupt (active high). 1 0111irqa is tri-state for no interrupt. irqa is logic 1 for active interrupt (active high, open source).
? ? ? ? XR16L651 2.5v, 3.3 and 5v low power uart with 32-byte fifo preliminary rev. p1.0.0 11 3.0 crystal oscillator or external clock. the 651 includes an on-chip oscillator (xtal1 and xtal2). the crystal oscillator provides the system clock to the baud rate generators (brg) in the uart. xtal1 is the input to the oscillator or external clock buffer input with xtal2 pin being the output. for programming details, see programmable baud rate generator on page 11 . the on-chip oscillator is designed to use an industry standard microprocessor crystal (parallel resonant, fundamental frequency with 10-22 pf capacitance load, esr of 20-80 ohms and 100ppm frequency tol- erance) connected externally between the xtal1 and xtal2 pins (see figure 7). alternatively, an external clock can be connected to the xtal1 pin to clock the internal baud rate generator for standard or custom rates. typically, the oscillator connections are shown in figure 7. for further reading on oscillator circuit please see application note dan108 on exars web site 3.1 p rogrammable b aud r ate g enerator the uart has its own baud rate generator (brg) with a prescaler for the transmiter. the prescaler is controlled by a software bit in the mcr register. the mcr register bit-7 sets the prescaler to divide the in- put crystal or external clock by 1 or 4. the clock out- put of the prescaler goes to the brg. the brg fur- ther divides this clock by a programmable divisor be- tween 1 and (2 16 -1) to obtain a 16x sampling clock of the serial data rate. the sampling clock is used by the transmitter for data bit shifting and receiver for da- ta sampling. the brg divisor (dll and dlm regis- ters) defaults to a random value upon power up or a reset . therefore, the brg must be programmed dur- ing initialization to the operating data rate. programming the baud rate generator registers dlm and dll provides the capability of selecting the operating data rate. table 3 shows the standard data rates available with a 14.7456 mhz crystal or external clock at 16x clock rate. when using a non-standard data rate crystal or external clock, the divisor value can be calculated for dll/dlm with the following equation. f igure 7. t ypical oscillator connections c1 22-47pf c2 22-47pf y1 1.8432 - 24 mhz r1 0-120 (optional) r2 500k - 1m xtal1 xtal2 f igure 8. b aud r ate g enerator xtal1 xtal2 crystal osc/ buffer mcr bit-7=0 (default) mcr bit-7=1 dll and dlm registers prescaler divide by 1 prescaler divide by 4 16x sam pling rate clock to transmitter baud rate generator logic divisor (decimal) = (xtal1 clock frequency / prescaler) / (serial data rate x 16)
XR16L651 ? ? ? ? 2.5v, 3.3v and 5v low power uart with 32-byte fifo rev. p1.0.0 preliminary 12 4.0 transmit and receive data the 651 uart has a transmit holding register (thr) and a receive holding register (rhr). the software driver must first separately read the lsr content for associated received data byte error flags before read- ing the receive data byte off the register rhr. that is because upon reading the rhr register the fifo pointer increments and points to next data byte. 4.1 fifo data loading and unloading through registers thr and rhr. the serial transmitter section consists of an 8-bit transmit hold register (thr) and transmit shift reg- ister (tsr). the status of the thr is provided in the line status register (lsr). writing to the thr trans- fers the contents of the data bus (d7-d0) to the thr, providing that the thr or tsr is empty. the thr empty flag in the lsr register will be set to a logic 1 when the transmitter is empty or when data is trans- ferred to the tsr. note that a write operation can be performed when the transmit holding register empty flag is set (logic 0 = at least one byte in fifo / thr, logic 1= fifo/thr empty). the serial receive section also contains an 8-bit re- ceive holding register, rhr. receive data is unload- ed by reading the rhr register. the receive section provides a mechanism to prevent false starts. on the falling edge of a start or false start bit, an internal re- ceiver counter starts counting clocks at 16x clock rate. after 7 1/2 clocks the start bit time should be shifted to the center of the start bit. at this time the start bit is sampled and if it is still a logic 0 it is validat- ed. evaluating the start bit in this manner prevents the receiver from assembling a false character. data byte error, if any, status is reported in lsr register. the thr and rhr register address is located at 0x00. transmit data byte is loaded to the thr when writting to address 0x00. receive data is unloaded from the rhr register when reading that same ad- dress location. 5.0 automatic rts hardware flow con- trol operation automatic rts hardware flow control is used to pre- vent data overrun to the local receiver fifo. the rts# output is used to request remote unit to sus- pend/resume data transmission. the auto rts flow control features is enabled to fit specific application requirement (see figure 9): - enable auto rts flow control using efr bit-6. - the auto rts function must be started by asserting rts output pin (mcr bit-0 or 1 to logic 1 after it is enabled. - enable rts interrupt through ier bit-6 (after setting efr bit-4). the uart issues an interrupt when the rts# pin makes a transition: isr bit-5 will be set to logic 1. with the auto rts function enabled, the rts# pin will not be de-asserted (logic 1) when the receive fifo t able 3: t ypical data rates with a 14.7456 mh z crystal or external clock o utput data rate mcr bit-7=1 o utput data rate mcr bit-7=0 d ivisor for 16x clock (decimal) d ivisor for 16x clock (hex) dlm p rogram v alue (hex) dll p rogram v alue (hex) d ata r ate e rror (%) 100 400 2304 900 09 00 0 600 2400 384 180 01 80 0 1200 4800 192 c0 00 c0 0 2400 9600 96 60 00 60 0 4800 19.2k 48 30 00 30 0 9600 38.4k 24 18 00 18 0 19.2k 76.8k 12 0c 00 0c 0 38.4k 153.6k 6 06 00 06 0 57.6k 230.4k 4 04 00 04 0 115.2k 460.8k 2 02 00 02 0 230.4k 921.6k 1 01 00 01 0
? ? ? ? XR16L651 2.5v, 3.3 and 5v low power uart with 32-byte fifo preliminary rev. p1.0.0 13 reaches the programmed trigger level, but will be de- asserted when the fifo reaches the next trigger level (see table 10). the rts# will be asserted again after the fifo is unloaded to the next trigger level below the programmed trigger level. however, even under these conditions, the 651 will continue to accept data until the receive fifo is full. 5.1 a uto cts f low c ontrol automatic cts flow control is used to prevent data overrun to the remote receiver fifo. the cts# input is monitored to suspend/restart the local transmitter. the auto cts flow control feature is selected to fit specific application requirement (see figure 9): - enable auto cts flow control using efr bit-7. - enable cts interrupt through ier bit-7 (after setting efr bit-4). the uart issues an interrupt when the cts# pin is de-asserted (logic 1): isr bit-5 will be set to 1, and uart will suspend transmission as soon as the stop bit of the character in process is shifted out. transmission is resumed after the cts# input is re-asserted (logic 0), indicating more data may be sent. f igure 9. a uto rts and cts f low c ontrol o peration the local uart (uarta) starts data transfer by asserting rtsa# (1). rtsa# is normally connected to ctsb# (2) of remote uart (uartb). ctsb# allows its transmitter to send data (3). txb data arrives and fills uarta receive fifo (4). when rxa data fills up to its receive fifo trigger level, uarta activates its rxa data ready interrupt (5) and con- tinues to receive and put data into its fifo. if interrupt service latency is long and data is not being unloaded, uarta monitors its receive data fill level to match the upper threshold of rts delay and de-assert rtsa# (6). ctsb# follows (7) and request uartb transmitter to suspend data transfer. uartb stops or finishes sending the data bits in its trans- mit shift register (8). when receive fifo data in uarta is unloaded to match the lower threshold of rts delay (9), uarta re-asserts rtsa# (10), ctsb# recognizes the change (11) and restarts its transmitter and data flow again until next receive fifo trigger (12). this same event applies to the reverse direction when uarta sends data to uartb with rtsb# and ctsa# controlling the data flow. rtsa# ctsb# rxa txb transmitter receiver fifo trigger reached auto rts trigger level auto cts monitor rtsa# txb rxa fifo ctsb# remote uart uartb local uart uarta on off on suspend restart rts high threshold data starts on off on assert rts# to begin transmission 1 2 3 4 5 6 7 receive data rts low threshold 9 10 11 receiver fifo trigger reached auto rts trigger level transmitter auto cts monitor rtsb# ctsa# rxb txa inta (rxa fifo interrupt) rx fifo trigger level rx fifo trigger level 8 12 rtscts1
XR16L651 ? ? ? ? 2.5v, 3.3v and 5v low power uart with 32-byte fifo rev. p1.0.0 preliminary 14 5.2 a utomatic s oftware f low c ontrol when software flow control is enabled (see table 12), the 651 compares compares one or two sequential receive data characters with the pro- grammed xon or xoff-1,2 character value(s). if re- ceive character(s) (rx) match the programmed val- ues, the 651 will halt transmission (tx) as soon as the current character has completed transmission. when a match occurs, the xoff (if enabled via ier bit-5) flag will be set and the interrupt output pin will be activated. following a suspension due to a match of the xoff characters values, the 651 will monitor the receive data stream for a match to the xon-1,2 char- acter value(s). if a match is found, the 651 will re- sume operation and clear the flags (isr bit-4). reset initially sets the contents of the xon/xoff 8-bit flow control registers to a logic 0. following reset the user can write any xon/xoff value desired for soft- ware flow control. different conditions can be set to detect xon/xoff characters (see table 12) and sus- pend/resume transmissions. when double 8-bit xon/ xoff characters are selected, the 651 compares two consecutive receive characters with two software flow control 8-bit values (xon1, xon2, xoff1, xoff2) and controls tx transmissions accordingly. under the above described flow control mechanisms, flow con- trol characters are not placed (stacked) in the user accessible rx data buffer or fifo. in the event that the receive buffer is overfilling and flow control needs to be executed, the 651 automati- cally sends an xoff message (when enabled) via the serial tx output to the remote modem. the 651 sends the xoff-1,2 characters two-character-times (= time taken to send two characters at the programmed baud rate) after the receive fifo crosses the pro- grammed trigger level. to clear this condition, the 651 will transmit the programmed xon-1,2 characters as soon as receive fifo drops to one trigger level below the programmed trigger level. table 4 below explains this: * after the trigger level is reached, an xoff character is sent after a short span of time ( = time required to send 2 characters); for example, after 2.083ms has elasped for 9600 baud and 10-bit word length setting. 5.3 s pecial c haracter d etect a special character detect feature is provided to de- tect an 8-bit character when bit-5 is set in the en- hanced feature register (efr). when this charac- ter (xoff2) is detected, it will be placed in the fifo along with normal incoming rx data. the 651 compares each incoming receive character with xoff-2 data. if a match exists, the received data will be transferred to fifo and isr bit-4 will be set to indicate detection of special character. although the internal register table shows each x-register with eight bits of character information, the actual number of bits is dependent on the programmed word length. line control register (lcr) bits 0-1 defines the num- ber of character bits, i.e., either 5 bits, 6 bits, 7 bits, or 8 bits. the word length selected by lcr bits 0-1 also determines the number of bits that will be used for the special character comparison. bit-0 in the x-registers corresponds with the lsb bit for the receive charac- ter. 5.4 i nfrared m ode the 651 uart includes the infrared encoder and de- coder compatible to the irda (infrared data associa- tion) version 1.0. the input pin enir conveniently ac- tivates the infrared mode. activating the enir pin pri- or to power up prevents the infrared light emitting di- ode (led) from turning on and drawing large amount of supply current while the system is powering up. the enir pin also sets the mcr register bit-6 to a 1. after power up or a reset, the software can overwrite mcr bit-6 if so desired. in the infrared mode, the user can choose to send/receive data either half-duplex or full-duplex. the half-duplex mode is chosen by setting bit-0 of xfr register to a 1. this prevents echoed data from reaching the receiver. when the infrared feature is enabled, the transmit data outputs, tx, idles at logic zero level. likewise, the rx input as- sumes an idle level of logic zero, see figure 10. the irda standard defines the infrared encoder sends out a 3/16 of a bit wide high-pulse for each 0 bit in the transmit data stream. this signal encoding reduc- t able 4: a uto x on /x off (s oftware ) f low c ontrol rx t rigger l evel int p in a ctivation x off c haracter ( s ) s ent ( characters in rx fifo ) x on c haracter ( s ) s ent ( characters in rx fifo ) 88 8* 0 16 16 16* 8 24 24 24* 16 28 28 28* 24
? ? ? ? XR16L651 2.5v, 3.3 and 5v low power uart with 32-byte fifo preliminary rev. p1.0.0 15 es the on-time of the infrared led, hence reduces the power consumption. see figure 10 below. the 651 has an additional feature to allow user to vary the transmit pulse width further reducing power con- sumption of the system where application permits (see irpw register for details). the wireless infrared decoder receives the input pulse from the infrared sensing diode on rx pin. each time it senses a light pulse, it returns a logic 0 to the data bit stream. the 651 also includes another feature - inversion of the ir pulse (xfr register bit-1), where each 0 bit in the data stream is transmitted (and received) as a low ir pulse. 5.5 dma o peration the XR16L651 fifo trigegr levels provide additional flexibility to the user for block mode operation. the user can optionally operate the transmit and receive fifos in the dma mode (fcr bit-3). the dma mode affects the state of the -rxrdy and -txrdy output pins. the following tables show this: 5.6 i nternal l oopback the 651 uart provides an internal loopback capabil- ity for system diagnostic purposes. the internal loop- back mode is enabled by setting mcr register bit-4 to logic 1. all regular uart functions operate normally. figure 11 shows how the modem port signals are re- configured. transmit data from the transmit shift reg- ister output is internally routed to the receive shift reg- f igure 10. i nfrared t ransmit d ata e ncoding and r eceive d ata d ecoding character data bits start stop 0000 0 11 111 bit time 1/16 clock delay irdecoder-1 rx data receive ir pulse (rx pin) character data bits start stop 0000 0 11 111 tx data transmit ir pulse (tx pin) bit time 1/2 bit time 3/16 bit time irencoder-1 t able 5: -rxrdy pin n on -dma m ode dma m ode 1 = fifo empty 0 to 1 transition when fifo empties 0 = at least 1 byte in fifo 1 to 0 transition when fifo reaches trigger level, or timeout occurs t able 6: -txrdy pin n on -dma m ode dma m ode 1 = at least 1 byte in fifo 1 = fifo is full 0 = fifo empty 0 = fifo has at least 1 empty location
XR16L651 ? ? ? ? 2.5v, 3.3v and 5v low power uart with 32-byte fifo rev. p1.0.0 preliminary 16 ister input allowing the system to receive the same data that it was sending. the tx pin is held at logic 1 or mark condition while rts# and dtr# are de-as- serted, and cts#, dsr# cd# and ri# inputs are ig- nored. 5.7 d evice i dentification and r evision the XR16L651 provides a device identification code and a device revision code to distinguish the part from others. to read the identification code from the part, it is required to set the baud rate generator reg- isters dll and dlm both to 0x00. now, reading the content of the dlm will provide 0x04 for the XR16L651 and reading the content of dll will pro- vide the revision of the part; for example, a reading of 0x01 means revision a. 5.8 s leep m ode & w ake - up i ndicator the 651 is designed to operate with low power con- sumption. a special sleep mode is included to further reduce power consumption when the chip is not be- ing used. with efr bit-4 and ier bit-4 enabled (set to a logic 1), the 651 enters the sleep mode but re- sumes normal operation when a start bit is detected, a change of state on any of the modem input pins rx, -ri, -cts, -dsr, -cd, or transmit data is provided by the user. if the sleep mode is enabled and the 651 is awakened by one of the conditions described above, an interrupt is issued by the 651 to signal to the cpu that it is awake. the interrupt source register (isr) will read a value of 0x01 for this interrupt and reading the isr clears this interrupt. since the same value is also used to indicate no pending interrupt, users should exercise caution while using the sleep mode. once awakened, the 651 will return to the sleep mode automatically after any other interrupting condi- tion (the true cause of waking up the 651) has been serviced. in any case, the sleep mode will not be en- tered while an interrupt is pending. the 651 will stay in the sleep mode of operation until it is disabled by setting ier bit-4 to a logic 0. 5.9 uart configuration registers. f igure 11. i nternal l oop b ack tx [7:0] r x [7:0] modem / general purpose control logic internal bus lines and control signals r ts# [7:0] mcr bit-4=1 vcc vcc vcc transmit shift register r eceive shift register c ts# [7:0] d tr # [7:0] d sr# [7:0] r i# [7:0] c d# [7:0] op1# op2# rts# cts# dtr# dsr# ri# cd#
? ? ? ? XR16L651 2.5v, 3.3 and 5v low power uart with 32-byte fifo preliminary rev. p1.0.0 17 the 651 has a set of configuration registers selected by address lines a0 to a2. the based page registers are 16c550 compatible with exar enhanced feature registers located on the second page (mirror) ad- dresses. the second page registers are only accessi- ble by setting lcr register to a value of 0xbf. the register set is shown on table 7 and table 8. t able 7: XR16L651 uart configuration registers a ddress r egister r ead /w rite c omments a2 a1 a0 16550 c ompatible r egisters 0 0 0 rhr - receive holding reg thr - transmit holding register read-only write-only lcr[7] = 0 0 0 0 dll - div latch low read/write lcr[7] = 1 0 0 1 dlm - div latch high read/write lcr[7] = 1 0 0 0 drev - device revision code read-only dll, dlm = 0x00 0 0 1 dvid - device identification code read-only dll, dlm = 0x00 0 0 1 ier - interrupt enable reg read/write lcr[7] = 0 0 1 0 isr - interrupt status reg fcr - fifo control reg read-only write-only 0 1 1 lcr - line control reg read/write 1 0 0 mcr - modem control reg read/write 1 0 1 lsr - line status reg reserved read-only write-only 1 1 0 msr - modem status reg reserved read-only write-only 1 1 1 spr - scratch pad reg read/write e nhanced r egisters 0 1 0 efr - enhanced function reg read/write lcr = 0xbf 1 0 0 xoff-1 - xoff character 1 read/write lcr = 0xbf 1 0 1 xoff-2 - xoff character 2 reserved read/write lcr = 0xbf 1 1 0 xon-1 - xon character 1 reserved read/write lcr = 0xbf 1 1 1 xon-2 - xon character 2 reserved read/write lcr = 0xbf
XR16L651 ? ? ? ? 2.5v, 3.3v and 5v low power uart with 32-byte fifo rev. p1.0.0 preliminary 18 . t able 8: uart configuration registers description. s haded bits are enabled when efr b it -4=1. a ddress a2-a0 r eg n ame r ead / w rite b it -7 b it -6 b it -5 b it -4 b it -3 b it -2 b it -1 b it -0 c omment 16c550 compatible registers 0 0 0 rhr rd bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 lcr[7]=0 0 0 0 thr wr bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 lcr[7]=0 0 0 0 dll rd/wr bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 lcr[7]=1 0 0 1 dlm rd/wr bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 lcr[7]=1 0 0 0 drev rd bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 dll, dlm = 0x00 0 0 1 dvid rd bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 dll, dlm = 0x00 0 0 1 ier rd/wr 0/ cts int. enable 0/ rts int. enable 0/ xoff int. enable sleep mode enable modem stat. int. enable rx line stat. int. enable tx empty int enable rx data int. enable lcr[7]=0 0 1 0 isr rd 0/ fifos enable 0/ fifos enable int source bit-5 int source bit-4 int source bit-3 int source bit-2 int source bit-1 int source bit-0 lcr[7]=x 0 1 0 fcr wr 0/ rx fifo trigger 0/ rx fifo trigger 0/ tx fifo trigger 0/ tx fifo trigger dma mode 1 enable tx fifo reset rx fifo reset fifos enable lcr[7]=x 0 1 1 lcr rd/wr divisor enable set tx break set par- ity even parity parity enable stop bits word length bit-1 word length bit-0 lcr[7]=x 1 0 0 mcr rd/wr 0/ brg pres- caler 0/ ir enable 0/ int type select internal lopback enable op2#/ irqn enable op1#/ rts# control dtr# control lcr[7]=x 1 0 1 lsr rd rx fifo e rror tsr empty thr empty rx break rx fram- ing error rx parity error rx data over- run rx data ready lcr[7]=x 1 0 1 xfr wr rsrvd rsrvd invert rs485 control output enable xonany lsr int mode auto rs485 int mode invert ir rx input enable half- duplex ir lcr[7]=x 1 1 0 msr rd cd ri dsr cts delta cd# delta ri# delta dsr# delta cts# lcr[7]=x irpw wr bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 lcr[7]=x 1 1 1 spr rd/wr bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 user data lcr[7]=x
? ? ? ? XR16L651 2.5v, 3.3 and 5v low power uart with 32-byte fifo preliminary rev. p1.0.0 19 5.10 t ransmitter the transmitter section comprises of an 8-bit trans- mit shift register (tsr) and 32 bytes of fifo which includes a byte-wide transmit holding register (thr). thr receives a data byte from the host (non- fifo mode) or a data byte from the fifo when the fifo is enabled by fcr bit-0. tsr shifts out every data bit with the 16x internal clock. a bit time is 16 clock periods. the transmitter sends the start-bit fol- lowed by the number of data bits, inserts the proper parity-bit if enabled, and adds the stop-bit(s). the sta- tus of the thr and tsr are reported in the line sta- tus register (lsr bit-5 and bit-6). 5.10.1 transmit holding register (thr) the transmit holding register is an 8-bit register pro- viding a data interface to the host processor. the host writes transmit data byte to the thr to be converted into a serial data stream including start-bit, data bits, parity-bit and stop-bit(s). the least-significant-bit (bit- 0) becomes first data bit to go out. the thr is the in- put register to the transmit fifo of 32 bytes when fifo operation is enabled by fcr bit-0. every time a write operation is made to the thr, its fifo data pointer is automatically bumped to the next sequential data location. a thr empty interrupt can be generat- ed when ier bit-1 is set to logic 1. 5.10.2 transmitter operation in non-fifo mode the host loads transmit data to thr one character at a time. the thr empty flag (lsr bit-5) is set when the data byte is transferred to tsr. thr flag can generate a transmit empty interrupt (isr bit-1) when it is enabled by ier bit-1. the tsr flag (lsr bit-6) is set when tsr becomes completely empty. enhanced registers 0 0 1 efr r/w auto cts enable auto rts enable special char select enable ier [7:4], isr [5:4], fcr[5:4], mcr[7:5] msr[7:4] irpw[7:0] xtra[7:0] soft- ware flow cntl bit-3 soft- ware flow cntl bit-2 soft- ware flow cntl bit-1 soft- ware flow cntl bit-0 lcr=0xbf 1 0 0 xoff1 r/w bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 lcr=0xbf 1 0 1 xoff2 r/w bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 lcr=0xbf 1 1 0 xon1 r/w bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 lcr=0xbf 1 1 1 xon2 r/w bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 lcr=0xbf t able 8: uart configuration registers description. s haded bits are enabled when efr b it -4=1. a ddress a2-a0 r eg n ame r ead / w rite b it -7 b it -6 b it -5 b it -4 b it -3 b it -2 b it -1 b it -0 c omment
XR16L651 ? ? ? ? 2.5v, 3.3v and 5v low power uart with 32-byte fifo rev. p1.0.0 preliminary 20 5.10.3 transmitter operation in fifo mode the host may fill the transmit fifo with up to 32 bytes of transmit data. the thr empty flag (lsr bit-5) is set whenever the fifo is empty. the thr empty flag can generate a transmit empty interrupt (isr bit-1) when the amount of data in the fifo falls below its programmed trigger level (see txtrg register). the transmit empty interrupt is enabled by ier bit-1. the tsr flag (lsr bit-6) is set when tsr/fifo becomes empty. furthermore, with the rs485 half-duplex di- rection control enabled (xfr bit-2 = 1), the source of the transmit empty interrupt changes to tsr empty instead of thr empty. this is to ensure the rts# output is not changed until the last stop bit of the last character is shifted out. 5.10.4 auto rs485 half-duplex control the auto rs485 half-duplex direction control chang- es the behavior of the transmitter when enabled by xfr bit-2. it de-asserts rts# output following the last stop bit of the last character that has been trans- mitted. this helps in turning around the transceiver to receive the remote stations response. the auto rs485 half-duplex direction contol also changes the transmitter empty interrupt to tsr empty instead of thr empty. when the host is ready to transmit next polling data packet again, it only has to load data bytes to the transmit fifo. the transmitter automati- cally re-asserts rts# output prior sending the data. f igure 12. t ransmitter o peration in non -fifo m ode transmit holding register (thr) transmit shift register (tsr) data byte l s b m s b thr interrupt (isr bit-1) enabled by ier bit-1 txnofifo1 16x or 8x clock (8xmode register)
? ? ? ? XR16L651 2.5v, 3.3 and 5v low power uart with 32-byte fifo preliminary rev. p1.0.0 21 5.11 r eceiver the receiver section contains an 8-bit receive shift register (rsr) and 32 bytes of fifo which includes a byte-wide receive holding register (rhr). the rsr uses the 16x clock for timing. it verifies and vali- dates every bit on the incoming character in the mid- dle of each data bit. on the falling edge of a start or false start bit, an internal receiver counter starts counting at the 16x clock rate. after 8 clocks the start bit period should be at the center of the start bit. at this time the start bit is sampled and if it is still a logic 0 it is validated. evaluating the start bit in this manner prevents the receiver from assembling a false charac- ter. the rest of the data bits and stop bits are sam- pled and validated in this same manner to prevent false framing. if there were any error(s), they are re- ported in the lsr register bits 1- 4. upon unloading the receive data byte from rhr, the receive fifo pointer is bumped and the error flags are immediately updated to reflect the status of the data byte in rhr register. rhr can generate a receive data ready in- terrupt upon receiving a character or delay until it reaches the fifo trigger level. furthemore, data de- livery to the host is guaranteed by a receive data ready time-out function when receive data does not reach the receive fifo trigger level. this time-out de- lay is 4 word lengths as defined by lcr[1,0] plus 12 bits time. the rhr interrupt is enabled by ier bit-0. 6.0 registers 6.1 r eceive h olding r egister (rhr) the receive holding register is a 8-bit register that holds a receive data byte from the receive shift regis- ter. it provides the receive data interface to the host processor. the host reads the receive data byte on this register whenever a data byte is trasferred from the rsr. the rhr register is part of the receive fifo of 32 bytes by 11-bit wide, the 3 extra bits are for the 3 error flags to be reported in lsr register. when the fifo is enabled by fcr bit-0, it acts as the first-out register of the fifo as new data are put over the first-in register. every time a read operation is made to the receive holding register, its fifo data pointer is automatically bumped to the next sequential data location. also, the error flags associated with the data byte are immediately updated onto the line sta- tus register (lsr) bits 2-4. 6.2 b aud r ate g enerator d ivisors (dll and dlm) the baud rate generator (brg) is a 16-bit counter that generates the data rate for the transmitter. the rate is programmed through registers dll and dlm which are only accessible when lcr bit-7 is set to 1. see programmable baud rate generator section for more details. f igure 13. t ransmiitter o peration in fifo and f low c ontrol m ode transmit data shift register (tsr) transmit data byte thr interrupt (isr bit-1) falls below the selected trigger level and then when becomes empty. fifo is enabled by fcr bit-0=1 transmit fifo (32-byte) txfifo1 16x clock auto cts flow control (cts# pin) auto software flow control flow control characters (xoff1/2 and xon1/2 reg.
XR16L651 ? ? ? ? 2.5v, 3.3v and 5v low power uart with 32-byte fifo rev. p1.0.0 preliminary 22 6.3 i nterrupt e nable r egister (ier) the interrupt enable register (ier) masks the inter- rupts from receive data ready, transmit empty, line status and modem status registers. these interrupts are reported in the interrupt status register (isr) register. 6.3.1 ier versus receive fifo interrupt mode operation when the receive fifo (fcr bit-0 = a logic 1) and receive interrupts (ier bit-0 = logic 1) are enabled, the rhr interrupts (see isr bits 2 and 3) status will reflect the following: a. the receive data available interrupts are issued to the host when the fifo has reached the pro- grammed trigger level. it will be cleared when the fifo drops below the programmed trigger level. b. fifo level will be reflected in the isr register when the fifo trigger level is reached. both the isr register status bit and the interrupt will be cleared when the fifo drops below the trigger level. c. the receive data ready bit (lsr bit-0) is set as soon as a character is transferred from the shift f igure 14. r eceiver o peration in non -fifo m ode receive data shift register (rsr) receive data byte and errors rhr interrupt (isr bit-2) receive data holding register (rhr) rxfifo1 16x clock receive data characters data bit validation error flags in lsr bits 4:2 f igure 15. r eceiver o peration in fifo and a uto rts f low c ontrol m ode receive data shift register (rsr) rxfifo1 16x clock error flags (32-sets) error flags in lsr bits 4:2 32 bytes by 11-bit wide fifo receive data characters fifo trigger=16 example: - rx fifo trigger level selected at 16 bytes data fills to 24 data falls to 8 data bit validation receive data fifo (32-byte) receive data receive data byte and errors rhr interrupt (isr bit-2) is programmed at fifo trigger level (rxtrg). fifo is enable by fcr bit-0=1 rts# de-asserts when data fills above the flow control trigger level to suspend remote transmitter. enable by efr bit-6=1, mcr bit-2. rts# re-asserts when data falls below the flow control trigger level to restart remote transmitter. enable by efr bit-6=1, mcr bit-2.
? ? ? ? XR16L651 2.5v, 3.3 and 5v low power uart with 32-byte fifo preliminary rev. p1.0.0 23 register to the receive fifo. it is reset when the fifo is empty. 6.3.2 ier versus receive/transmit fifo polled mode operation when fcr bit-0 equals a logic 1 for fifo enable; re- setting ier bits 0-3 enables the XR16L651 in the fifo polled mode of operation. since the receiver and transmitter have separate bits in the lsr either or both can be used in the polled mode by selecting respective transmit or receive control bit(s). a. lsr bit-0 indicates there is data in rhr or rx fifo. b. lsr bit 1-4 provides the type of receive data er- rors encountered for the data byte in rhr, if any. c. lsr bit-5 indicates thr is empty. d. lsr bit-6 indicates when both the transmit fifo and tsr are empty. e. lsr bit-7 indicates the wire-or function of all errors in the rx fifo. ier[0]: rhr interrupt enable the receive data ready interrupt will be issued when rhr has a data character in the non-fifo mode or when the receive fifo has reached the programmed trigger level in the fifo mode. logic 0 = disable the receive data ready interrupt. (default) logic 1 = enable the receiver data ready interrupt. ier[1]: thr interrupt enable this bit enables the transmit ready interrupt which is issued whenever the thr becomes empty or when data in the fifo falls below the programmed trigger level. logic 0 = disable transmit holding register empty in- terrupt. (default) logic 1 = enable transmit holding register empty in- terrupt. ier[2]: receive line status interrupt enable any change of state of the lsr register bits 1,2,3 or 4 will generate an interrupt to inform the host controller about the error status of the current data byte in fifo. logic 0 = disable the receiver line status interrupt. (default) logic 1 = enable the receiver line status interrupt. ier[3]: modem status interrupt enable logic 0 = disable the modem status register interrupt. (default) logic 1 = enable the modem status register interrupt. ier[4]: sleep mode enable (requires efr bit-4 = 1) logic 0 = disable sleep mode (default). logic 1 = enable sleep mode. see sleep mode sec- tion for further details. ier[5]: xoff interrupt enable (requires efr bit- 4=1) logic 0 = disable the software flow control, receive xoff interrupt. (default) logic 1 = enable the software flow control, receive xoff interrupt. see software flow control section for details. ier[6]: rts# output interrupt enable (requires efr bit-4=1) logic 0 = disable the rts# interrupt. (default ). logic 1 = enable the rts# interrupt. the uart is- sues an interrupt when the rts# pin makes a transi- tion. ier[7]: cts# input interrupt enable (requires efr bit-4=1) logic 0 = disable the cts# interrupt. (default). logic 1 = enable the cts# interrupt. the uart is- sues an interrupt when cts# pin makes a transition. 6.4 i nterrupt s tatus r egister (isr) the uart provides multiple levels of prioritized inter- rupts to minimize external software interaction. the interrupt status register (isr) provides the user with six interrupt status bits. performing a read cycle on the isr will give the user the current highest pending interrupt level to be serviced, others queue up for next service. no other interrupts are acknowledged until the pending interrupt is serviced. the interrupt source table, table 9, shows the data values (bit 0-5) for the six prioritized interrupt levels and the interrupt sources associated with each of these interrupt lev- els. 6.4.1 interrupt generation: ? lsr is by any of the lsr bits 1, 2, 3 and 4. ? rxrdy is by rx trigger level. ? rxrdy time-out is by the a 4-char plus 12 bits delay timer if data doesnt reach fifo trigger level. ? txrdy is by lsr bit-5 (or bit-6 in auto rs485 con- trol). ? msr is by any of the msr bits, 0, 1, 2 and 3. ? receive xoff/special character is by detection of a xoff or special character.
XR16L651 ? ? ? ? 2.5v, 3.3v and 5v low power uart with 32-byte fifo rev. p1.0.0 preliminary 24 ? cts# is by a change of state on the input pin with auto flow control enabled, efr bit-7, and depend- ing on selection on mcr bit-2. ? rts# is when its receiver changes the state of the output pin during auto rts flow control enabled by efr bit-6 and selection of mcr bit-2. 6.4.2 interrupt clearing: ? lsr interrupt is cleared by a read to the lsr regis- ter. ? rxrdy and rxrdy time-out are cleared by read- ing data until fifo falls below the trigger level. ? txrdy interrupt is cleared by a read to the isr register. ? msr interrupt is cleared by a read to the msr reg- ister. ? xoff or special character interrupt is cleared by a read to isr. ? rts# and cts# status change interrupts are cleared by a read to the msr register. isr[0]: interrupt status logic 0 = an interrupt is pending and the isr con- tents may be used as a pointer to the appropriate in- terrupt service routine. logic 1 = no interrupt pending. (default condition) isr[3:1]: interrupt status these bits indicate the source for a pending interrupt at interrupt priority levels 1, 2, 3 and 4 (see interrupt source table 9). isr[5:4]: interrupt status these bits are enabled when efr bit-4 is set to a log- ic 1. isr bit-4 indicates that the receiver detected a data match of the xoff character(s). n ote : note that once set to a logic 1, the isr bit-4 will stay a logic 1 until a xon character is received. isr bit-5 indi- cates that cts# or rts# has changed state. isr[7:6]: fifo enable status these bits are set to a logic 0 when the fifos are disabled. they are set to a logic 1 when the fifos are enabled. 6.5 fifo c ontrol r egister (fcr) this register is used to enable the fifos, clear the fifos, set the transmit/receive fifo trigger levels, and select the dma mode. the dma, and fifo modes are defined as follows: fcr bit-0: tx and rx fifo enable logic 0 = disable the transmit and receive fifo. (de- fault). logic 1 = enable the transmit and receive fifos. this bit must be set to logic 1 when other fcr bits are written or they will not be programmed. fcr[1]: rx fifo reset this bit is only active when fcr bit-0 is a 1. logic 0 = no receive fifo reset. (default) logic 1 = reset the receive fifo pointers and fifo level counter logic (the receive shift register is not cleared or altered). this bit will return to a logic 0 after resetting the fifo. fcr[2]: tx fifo reset this bit is only active when fcr bit-0 is a 1. logic 0 = no transmit fifo reset. (default) t able 9: i nterrupt s ource and p riority l evel p riority isr r egister s tatus b its s ource of interrupt + l evel b it -5 b it -4 b it -3 b it -2 b it -1 b it -0 1 0 0 0 1 1 0 lsr (receiver line status register) 2 0 0 0 1 0 0 rxrdy (received data ready) 3 0 0 1 1 0 0 rxrdy (receive data time-out) 4 0 0 0 0 1 0 txrdy ( transmitter holding register empty) 5 0 0 0 0 0 0 msr (modem status register) 6 0 1 0 0 0 0 rxrdy (received xoff or special character) 7 1 0 0 0 0 0 cts#/dsr#, rts#/dtr# change of state - 0 0 0 0 0 1 none (default)
? ? ? ? XR16L651 2.5v, 3.3 and 5v low power uart with 32-byte fifo preliminary rev. p1.0.0 25 logic 1 = reset the transmit fifo pointers and fifo level counter logic (the transmit shift register is not cleared or altered). this bit will return to a logic 0 after resetting the fifo. fcr[3]: dma mode select controls the behavior of the -txrdy and -rxrdy pins. see dma operation section for details. logic 0 = set dma to mode 0. (default) logic 1 = set dma to mode 1. fcr[5:4]: transmit fifo trigger select (logic 0 = default, tx trigger level = one) these 2 bits set the trigger level for the transmit fifo interrupt. the uart will issue a transmit interrupt when the number of characters in the fifo falls be- low the selected trigger level, or when it gets empty in case that the fifo did not get filled over the trigger level on last re-load. table 10 below shows the selec- tions. efr bit-4 must be set to 1 before these bits can be accessed. fcr[7:6]: receive fifo trigger select (logic 0 = default, rx trigger level =1). the fctr bits 6-7 are associated with these 2 bits. these 2 bits are used to set the trigger level for the receiver fifo interrupt. table 10 shows the complete selections. . 6.6 l ine c ontrol r egister (lcr) the line control register is used to specify the asyn- chronous data communication format. the word or character length, the number of stop bits, and the par- ity are selected by writing the appropriate bits in this register. lcr[1-0]: tx and rx word length select these two bits specify the word length to be transmit- ted or received. t able 10: t ransmit and r eceive fifo t rigger l evel s election with auto rts hysteresis fcr b it -7 fcr b it -6 fcr b it -5 fcr bit -4 t ransmit int t rigger l evel r eceive int t rigger l evel a uto rts d e - assert a uto rts r e - assert c ompatibility 0 0 1 1 0 1 0 1 0 0 1 1 0 1 0 1 16 8 24 30 8 16 24 28 16 24 28 28 0 8 16 24 16c650a compati- ble. bit-1 bit-0 w ord length 0 0 5 (default) 01 6 10 7 11 8
XR16L651 ? ? ? ? 2.5v, 3.3v and 5v low power uart with 32-byte fifo rev. p1.0.0 preliminary 26 lcr[2]: tx and rx stop-bit length select the length of stop bit is specified by this bit in con- junction with the programmed word length. lcr[3]: tx and rx parity select parity or no parity can be selected via this bit. the parity bit is a simple way used in communications for data integrity check. see table 11 for parity selection summary below. ? logic 0 = no parity. ? logic 1 = a parity bit is generated during the trans- mission while the receiver checks for parity error of the data character received. lcr[4]: tx and rx parity select if the parity bit is enabled with lcr bit-3 set to a logic 1, lcr bit-4 selects the even or odd parity format. logic 0 = odd parity is generated by forcing an odd number of logic 1s in the transmitted character. the receiver must be programmed to check the same for- mat. (default). ? logic 1 = even parity is generated by forcing an even the number of logic 1s in the transmitted char- acter. the receiver must be programmed to check the same format. lcr[5]: tx and rx parity select if the parity bit is enabled, lcr bit-5 selects the forced parity format. ? lcr bit-5 = logic 0, parity is not forced. (default) ? lcr bit-5 = logic 1 and lcr bit-4 = logic 0, parity bit is forced to a logical 1 for the transmit and receive data. ? lcr bit-5 = logic 1 and lcr bit-4 = logic 1, parity bit is forced to a logical 0 for the transmit and receive data. lcr[6]: transmit break enable ? when enabled the break control bit it causes a break condition to be transmitted (the tx output is forced to a space, logic 0, state). this condition remains until disabled by setting lcr bit-6 to a logic 0. ? logic 0 = no tx break condition. (default) ? logic 1 = forces the transmitter output (tx) to a space, logic 0, for alerting the remote receiver of a line break condition. lcr[7]: baud rate divisors enable baud rate generator divisor (dll/dlm) enable. ? logic 0 = data registers are selected. (default) ? logic 1 = divisor latch registers are selected. 6.7 m odem c ontrol r egister (mcr) or g en - eral p urpose o utputs c ontrol . the mcr register is used for controlling the serial/ modem interface signals or general purpose inputs/ outputs. mcr[0]: dtr# pins the dtr# pin is a modem control output. if the mo- dem interface is not used, this output may be used for general purpose. ? logic 0 = force dtr# output to a logic 1. (default) ? logic 1 = force dtr# output to a logic 0. bit-2 w ord length s top bit length (b it time ( s )) 0 5,6,7,8 1 (default) 1 5 1-1/2 16,7,8 2 t able 11: p arity selection lcr b it -5 lcr b it -4 lcr b it - 3 p arity selection xx0 no parity 0 0 1 odd parity 0 1 1 even parity 1 0 1 force parity to mark, 1 1 1 1 forced parity to space, 0
? ? ? ? XR16L651 2.5v, 3.3 and 5v low power uart with 32-byte fifo preliminary rev. p1.0.0 27 mcr[1]: rts# pins the rts# pin is a modem control output and may be used for automatic hardware flow control by enabled by efr bit-6. if the modem interface is not used, this output may be used for general purpose. ? logic 0 = force rts# output to a logic 1. (default) ? logic 1 = force rts# output to a logic 0. mcr[2]: op1# output op1# is a general purpose output. ? logic 0 = op1# output is at logic 1. ? logic 1 = op1# output is at logic 0 mcr[3]: op2# or irqn enable during pc mode op2# is a general purpose output available during the intel or motorola bus interface mode of operation. in the pc bus mode, it enables the irqn operation. see pc mode section. during intel or motorola bus mode operation: ? logic 0 = op2# output is at logic 1. ? logic 1 = op2# output is at logic 0. during pc mode operation: ? logic 0 = disable irqn operation. (default). ? logic 1 = enable irqn operation. mcr[4]: internal loopback enable ? logic 0 = disable loopback mode. (default) ? logic 1 = enable local loopback mode, see loop- back section and figure 11. mcr[5]: active/tristate interrupt output enable ? logic 0 = enable active or tristate interrupt output (default). ? logic 1 = enable open source interrupt output mode. see table 2 for detailed information. mcr[6]: infrared encoder/decoder enable logic 0 is the default unless the ir mode is forced by the enir pin. this bit can overwrite the enir state af- ter a power up or reset. ? logic 0 = enable the standard modem receive and transmit input/output interface. (default) ? logic 1 = enable infrared irda receive and transmit inputs/outputs. the tx/rx output/input are routed to the infrared encoder/decoder. the data input and output levels conform to the irda infrared interface requirement. the infrared tx output is at logic 0 during idle condition. the infrared receive data input polarity is also logic 0, however, it may be inverted when using an infrared modules that pro- vides inverted signal output. use register xfr bit-1 to invert the receive input signal level going to the infrared decoder. also see xfr bit-0 for half-duplex operation where the receiver can be disabled while transmiting. mcr[7]: clock prescaler select ? logic 0 = divide by one. the input clock from the crystal or external clock is fed directly to the pro- grammable baud rate generator without further modification, i.e., divide by one. (default). ? logic 1 = divide by four. the prescaler divides the input clock from the crystal or external clock by four and feeds it to the programmable baud rate gen- erator, hence, data rates become one forth. 6.8 l ine s tatus r egister (lsr) - r ead o nly this register provides the status of data transfers be- tween the uart and the host. lsr[0]: receive data ready indicator ? logic 0 = no data in receive holding register or fifo. (default). ? logic 1 = data has been received and is saved in the receive holding register or fifo. lsr[1]: receiver overrun flag ? logic 0 = no overrun error. (default) ? logic 1 = overrun error. a data overrun error condi- tion occurred in the receive shift register. this hap- pens when additional data arrives while the fifo is full. in this case the previous data in the receive shift register is overwritten. note that under this condition the data byte in the receive shift register is not transferred into the fifo, therefore the data in the fifo is not corrupted by the error. lsr[2]: receive data parity error flag ? logic 0 = no parity error. (default) ? logic 1 = parity error. the receive character in rhr does not have correct parity information and is sus- pect. this error is associated with the character available for reading in rhr. lsr[3]: receive data framing error flag ? logic 0 = no framing error. (default) ? logic 1 = framing error. the receive character did not have a valid stop bit(s). this error is associated with the character available for reading in rhr. lsr[4]: receive break flag ? logic 0 = no break condition. (default) ? logic 1 = the receiver received a break signal (rx was a logic 0 for at least one character frame time). in the fifo mode, only one break character is loaded into the fifo. the break indication remains
XR16L651 ? ? ? ? 2.5v, 3.3v and 5v low power uart with 32-byte fifo rev. p1.0.0 preliminary 28 until the rx input returns to the idle condition, mark or logic 1. lsr[5]: transmit holding register empty flag this bit is the transmit holding register empty indi- cator. this bit indicates that the transmitter is ready to accept a new character for transmission. in addition, this bit causes the uart to issue an interrupt to the host when the thr interrupt enable is set. the thr bit is set to a logic 1 when the last data byte is trans- ferred from the transmit holding register to the trans- mit shift register. the bit is reset to logic 0 concurrent- ly with the data loading to the transmit holding regis- ter by the host. in the fifo mode this bit is set when the transmit fifo is empty, it is cleared when the transmit fifo contains at least 1 byte. lsr[6]: transmit shift register empty flag this bit is the transmit shift register empty indicator. this bit is set to a logic 1 whenever the transmitter goes idle. it is set to logic 0 whenever either the thr or tsr contains a data character. in the fifo mode this bit is set to one whenever the transmit fifo and transmit shift register are both empty. lsr[7]: receive fifo data error flag ? logic 0 = no fifo error. (default) ? logic 1 = a global indicator for the sum of all error bits in the rx fifo. at least one parity error, fram- ing error or break indication is in the fifo data. this bit clears when there is no more error(s) in the fifo. 6.9 e xtra f eature r egister (xfr) - w rite o nly this register provides additonal features and controls to the XR16L651 uart. xfr [0]: half-duplex infrared mode enable when infrared mode is enabled, mcr bit-6=1, this bit selects the infrared mode to operate in normal full-du- plex or half-duplex mode. this half-duplex mode fea- ture is very desirable when user does not want to see his own sending data that are echoed through the reflection of lights. ? logic 0 = disable. the receiver is active during data transmission. ? logic 1 = enabled half-duplex operation. the infra- red receiver is disabled during data transmission. xfr [1]: invert received infrared input signal this bit controls the input polarity of the infrared data. ? logic 0 = infrared data input idles at logic 0. (default) ? logic 1 = infrared data idles at logic 1, pulses low. xfr [2]: auto rs485 enable this bit enables the auto rs485 direction control fea- ture for half-duplex operation with rs-485 transceiv- er. the feature should only be enabled when normal rts# output and auto rts flow control are not in used. ? logic 0 = disable the auto rs485 direction control function. this allows normal rts# output or auto rts flow control operation. ? logic 1 = enable the auto rs485 direction function. the rts# output will automatically change its logic state to control the rs-485 transceiver from send- ing and receiving. also see xfr bit-5 and section 5.6.3. xfr [3]: lsr bad data interrupt operation when the lsr interrupt is enabled, ier bit-2=1, this bit selects when the interrupt pin (int) will report re- ceived character error: parity, framing or break. use this feature only if application needs immediate knowledge when a bad character is received. ? logic 0 = received data error interrupt (lsr inter- rupt) will be generated when the bad character is available for reading from the fifo. this is compat- ible to industry standard 16c550 operation. ? logic 1 = received data error interrupt (lsr inter- rupt) is generated immediately upon receipt of the bad character. it will be reset when lsr is read. if user does not read the bad character out, another bad character interrupt is generated when its avail- able for reading from the fifo. xfr [4]: xonany enable this bit enables and disables the xon-any function when xon/xoff software flow control is enabled. ? logic 0 = disable the xon-any function. ? logic 1 = enable the xon-any function. the receiver will use any received character as an xon character and resume data transmission. xfr [5]: invert auto rs-485 control output when auto rs485 feature is enabled, xfr bit-2=1, rts# output automatically changes its logic state to control the rs-485 transceiver. ? logic 0 = during auto rs-485, rts# control output signal to the transceiver is logic 1 for transmit and logic 0 for receive. ? logic 1 = the rts# output control signal to the transceiver is logic 0 for transmit and logic 1 for receive. user must assert rts# for operation to take effect. xfr [7:6] not used, reserved.
? ? ? ? XR16L651 2.5v, 3.3 and 5v low power uart with 32-byte fifo preliminary rev. p1.0.0 29 6.10 m odem s tatus r egister (msr) - r ead o nly this register provides the current state of the modem interface signals, or other peripheral device that the uart is connected. lower four bits of this register are used to indicate the changed information. these bits are set to a logic 1 whenever a signal from the modem changes state. these bits may be used as general purpose inputs/outpus when they are not used with modem signals. msr[0]: delta cts# input flag ? logic 0 = no change on cts# input (default). ? logic 1 = the cts# input has changed state since the last time it was monitored. a modem status interrupt will be generated if msr interrupt is enabled (ier bit-3. msr[1]: delta dsr# input flag ? logic 0 = no change on dsr# input (default). ? logic 1 = the dsr# input has changed state since the last time it was monitored. a modem status interrupt will be generated if msr interrupt is enabled (ier bit-3. msr[2]: delta ri# input flag ? logic 0 = no change on ri# input (default). ? logic 1 = the ri# input has changed from a logic 0 to a logic 1, ending of the ringing signal. a modem status interrupt will be generated if msr interrupt is enabled (ier bit-3. msr[3]: delta cd# input flag ? logic 0 = no change on cd# input (default). ? logic 1 = indicates that the cd# input has changed state since the last time it was monitored. a modem status interrupt will be generated if msr interrupt is enabled (ier bit-3. msr[4]: cts input status cts# pin may function as automatic hardware flow control signal input if it is enabled and selected by au- to cts (efr bit-7). auto cts flow control allows starting and stopping of local data transmissions based on the modem cts# signal. a logic 1 on the cts# pin will stop uart transmitter as soon as the current character has finished transmission, and a logic 0 will resume data transmission. normally msr bit-4 bit is the compliment of the cts# input. however in the loopback mode, this bit is equivalent to the rts# bit in the mcr register. the cts# input may be used as a general purpose input when the modem in- terface is not used. msr[5]: dsr input status dsr# (active high, logical 1). normally this bit is the compliment of the dsr# input. in the loopback mode, this bit is equivalent to the dtr# bit in the mcr regis- ter. the dsr# input may be used as a general pur- pose input when the modem interface is not used. msr[6]: ri input status ri# (active high, logical 1). normally this bit is the compliment of the ri# input. in the loopback mode this bit is equivalent to bit-2 in the mcr register. the ri# input may be used as a general purpose input when the modem interface is not used. msr[7]: cd input status cd# (active high, logical 1). normally this bit is the compliment of the cd# input. in the loopback mode this bit is equivalent to bit-3 in the mcr register. the cd# input may be used as a general purpose input when the modem interface is not used. 6.11 i nfrared t ransmit p ulse w idth c ontrol r egister (irpw) - w rite o nly the irpw register allows the user to program the the encoders pulse width. this cuts the led on-time, hence, reducing power consumption. irpw [7:0]: pulse width control. a 0x00 value (default) will set the pulse width to nor- mal width of 3/16 of the data bit rate. the programma- ble infrared pulse width can be calculated using the following equation: infrared pulse width (pw) = crystal clock period x n, where n is the value in irpw from 1 to 255. examples: crystal frequency = 14.7456mhz (clock period of 67.82ns) pw = 67.82 x n or ranges from 67.82ns to 17.29ms caution: never allow pw to exceed the operating da- ta rate bit period, else the encoder stops. 6.12 s cratch p ad r egister (spr) this is a 8-bit general purpose register for the user to store temporary data. the content of this register is preserved during sleep mode but becomes 0xff (de- fault) after a reset or a power off-on cycle. 6.13 b aud r ate g enerator r egisters (dll and dlm) the concatenation of the contents of dlm and dll gives the 16-bit divisor value which is used to calcu- late the baud rate: ? baud rate = (clock frequency / 16) / divisor see mcr bit-7 and the baud rate table also.
XR16L651 ? ? ? ? 2.5v, 3.3v and 5v low power uart with 32-byte fifo rev. p1.0.0 preliminary 30 6.14 d evice i dentification r egister (dvid) - r ead o nly this register contains the device id (0x04 for XR16L651). prior to reading this register, dll and dlm should be set to 0x00. 6.15 d evice r evision r egister (drev) - r ead o nly this register contains the device revision information. for example, 0x01 means revision a. prior to reading this register, dll and dlm should be set to 0x00. 6.16 e nhanced f eature r egister (efr) enhanced features are enabled or disabled using this register. bit 0-3 provide single or dual consecutive character software flow control selection (see table 12). when the xon1 and xon2 and xoff1 and xoff2 modes are selected, the double 8-bit words are concatenated into two sequential characters. cau- tion: note that whenever changing the tx or rx flow control bits, always reset all bits back to logic 0 (dis- able) before programming a new setting. efr bit 0-3: software flow control select combinations of software flow control can be select- ed by programming these bits. efr[4]: enhanced function bits enable enhanced function control bit. this bit enables ier bits 4-7, isr bits 4-5, fcr bits 4-5, mcr bits 5-7, xfr bits 0-7 and irpw bits 0-7 to be modified. after modifying any enhanced bits, efr bit-4 can be set to a logic 0 to latch the new values. this feature pre- vents legacy software from altering or overwriting the enhanced functions once set. normally, it is recom- mended to leave it enabled, logic 1. ? logic 0 = modification disable/latch enhanced fea- tures. ier bits 4-7, isr bits 4-5, fcr bits 4-5, mcr bits 5-7, xfr bits 0-7 and irpw bits 0-7 are saved to retain the user settings. after a reset, the ier bits 4-7, isr bits 4-5, fcr bits 4-5, mcr bits 5-7, xfr bits 0-7 and irpw bits 0-7 are set to a logic 0 to be compatible with st16c554 mode. (default). ? logic 1 = enables the above-mentioned register bits to be modified by the user. efr[5]: special character detect enable ? logic 0 = special character detect disabled. (default) ? logic 1 = special character detect enabled. the uart compares each incoming receive character t able 12: s oftware f low c ontrol f unctions efr bit -3 c ont -3 efr bit -2 c ont -2 efr bit -1 c ont -1 efr bit -0 c ont -0 t ransmit and r eceive s oftware f low c ontrol 0 0 0 0 no tx and rx flow control (default and reset) 0 0 x x no transmit flow control 1 0 x x transmit xon1/xoff1 0 1 x x transmit xon2/xoff2 1 1 x x transmit xon1 and xon2/xoff1 and xoff2 x x 0 0 no receive flow control x x 1 0 receiver compares xon1/xoff1 x x 0 1 receiver compares xon2/xoff2 1 0 1 1 transmit xon1/ xoff1, receiver compares xon1 or xon2, xoff1 or xoff2 0 1 1 1 transmit xon2/xoff2, receiver compares xon1 or xon2, xoff1 or xoff2 1 1 1 1 transmit xon1 and xon2/xoff1 and xoff2, receiver compares xon1 and xon2/xoff1 and xoff2 0 0 1 1 no transmit flow control, receiver compares xon1 and xon2/xoff1 and xoff2
? ? ? ? XR16L651 2.5v, 3.3 and 5v low power uart with 32-byte fifo preliminary rev. p1.0.0 31 with data in xoff-2 register. if a match exists, the received data will be transferred to fifo and isr bit-4 will be set to indicate detection of the special character. bit-0 corresponds with the lsb bit for the receive character. if flow control is set for compar- ing xon1, xoff1 (efr [1:0]=10) then flow control and special character work normally. however, if flow control is set for comparing xon2, xoff2 (efr[1:0]=01) then flow control works normally, but xoff2 will not go to the fifo, and will generate an xoff interupt and a special character interrupt. efr[6]: auto rts flow control enable rts# output may be used for hardware flow control by setting efr bit-6 to logic 1. when auto rts is se- lected, an interrupt will be generated when the re- ceive fifo is filled to the programmed trigger level and rts de-asserts to a logic 1 at the next upper trig- ger level. rts# will return to a logic 0 when fifo da- ta falls below the next lower trigger level. the rts# output must be asserted (logic 0) before the auto rts can take effect. rts# pin will function as a general purpose output when hardware flow control is dis- abled. ? logic 0 = automatic rts flow control is disabled. (default) ? logic 1 = enable automatic rts flow control. efr[7]: auto cts flow control enable automatic cts flow control. ? logic 0 = automatic cts flow control is disabled. (default) ? logic 1 = enable automatic cts flow control. data transmission stops when cts# input de-asserts to logic 1. data transmission resumes when cts# input returns to a logic 0. t able 13: uart reset conditions registers reset state dll bits 7-0 = 0xxx dlm bits 7-0 = 0xxx rhr bits 7-0 = 0xxx thr bits 7-0 = 0xxx ier bits 7-0 = 0x00 fcr bits 7-0 = 0x00 isr bits 7-0 = 0x01 lcr bits 7-0 = 0x00 mcr bits 7-0 = 0x00 lsr bits 7-0 = 0x60 xfr bits 7-0 = 0x00 msr bits 3-0 = logic 0 bits 7-4 = logic levels of the inputs irpw bits 7-0 = 0x00 spr bits 7-0 = 0xff efr bits 7-0 = 0x00 xon1 bits 7-0 = 0x00 xon2 bits 7-0 = 0x00 xoff1 bits 7-0 = 0x00 xoff2 bits 7-0 = 0x00 i/o signals reset state tx normal = logic 1 infrared = logic 0 rts# logic 1 dtr# logic 1
XR16L651 ? ? ? ? 2.5v, 3.3v and 5v low power uart with 32-byte fifo rev. p1.0.0 preliminary 32 absolute maximum ratings power supply range 7 volts voltage at any pin -0.5 to 7v operating temperature -40 o to +85 o c storage temperature -65 o to +150 o c package dissipation 500 mw thermal resistance (7x7x1.4mm 48-tqfp) theta-ja = 59 o c/w, theta-jc = 16 o c/w electrical characteristics (preliminary) dc electrical characteristics for 2.5v signaling u nless otherwise noted : ta=0 o to 70 o c (-40 o to +85 o c for industrial grade package ), v cc is 2.5 +/- 10% s ymbol p arameter m in m ax u nits c ondition n otes v il input low voltage -0.3 0.6 v v ih input high voltage 2.0 6.0 v v ol output low voltage tbd v v oh output high voltage tbd v i il input low leakage current +/-10 ua i ih input high leakage current +/-10 ua c in input pin capacitance 5 pf i cc power supply current 1.0 ma crystal or external clock of 12mhz i sleep sleep current 100 ua uart at asleep. a2-a0 at gnd, all inputs at vcc or gnd
? ? ? ? XR16L651 2.5v, 3.3 and 5v low power uart with 32-byte fifo preliminary rev. p1.0.0 33 ac electrical characteristics for 2.5v signalling u nless otherwise noted : ta=0 o to 70 o c (-40 o to +85 o c for industrial grade package ), v cc is 2.5v +/- 10% s ymbol p arameter m in m ax u nit n otes osc crystal oscillator 16 mhz clk external clock 24 mhz t as address valid to cs# asserted 15 ns t ah cs# de-asserted to address invalid 10 ns t dly delay between cs# active cycles (16 mode) 50 ns t rd read strobe width (16 mode) 50 ns t wr write strobe width (16 mode) 50 ns t da read/write asserted to data valid 50 ns t dh read/write de-asserted to data invalid 50 ns t rws r/w# valid to cs# valid (68 mode) tbd ns t rwh cs# de-asserted to r/w# de-asserted (68 mode) tbd ns t csl cs# active width tbd ns t csh cs# inactive width tbd ns t 17d delay from iow# to output 50 ns t 18d delay to set interrupt from modem input 50 ns t 19d delay to reset interrupt from ior# 50 ns
XR16L651 ? ? ? ? 2.5v, 3.3v and 5v low power uart with 32-byte fifo rev. p1.0.0 preliminary 34 dc electrical characteristics for 3.3v signaling u nless otherwise noted : ta=0 o to 70 o c (-40 o to +85 o c for industrial grade package ), v cc is 3.3v +/- 10% s ymbol p arameter m in m ax u nits c ondition n otes v il input low voltage -0.3 0.8 v v ih input high voltage 2.0 6.0 v v ol output low voltage tbd v v oh output high voltage tbd v i il input low leakage current +/-10 ua i ih input high leakage current +/-10 ua c in input pin capacitance 5 pf i cc power supply current 1.0 ma crystal or external clock of 16mhz i sleep sleep current 100 ua uart at asleep. a2-a0 at gnd, all inputs at vcc or gnd
? ? ? ? XR16L651 2.5v, 3.3 and 5v low power uart with 32-byte fifo preliminary rev. p1.0.0 35 ac electrical characteristics for 3.3v signaling u nless otherwise noted : ta=0 o to 70 o c (-40 o to +85 o c for industrial grade package ), v cc is 3.3v +/- 10% s ymbol p arameter m in m ax u nit n otes osc crystal oscillator 20 mhz clk external clock 33 mhz t as address valid to cs# asserted 15 ns t ah cs# de-asserted to address invalid 10 ns t dly delay between cs# active cycles (16 mode) 50 ns t rd read strobe width (16 mode) 50 ns t wr write strobe width (16 mode) 50 ns t da read/write asserted to data valid 50 ns t dh read/write de-asserted to data invalid 50 ns t rws r/w# asserted to cs# asserted (68 mode) tbd ns t rwh cs# de-asserted to r/w# de-asserted (68 mode) tbd ns t csl cs# active width tbd ns t csh cs# inactive width tbd ns t 17d delay from iow# to output 50 ns t 18d delay to set interrupt from modem input 50 ns t 19d delay to reset interrupt from ior# 50 ns
XR16L651 ? ? ? ? 2.5v, 3.3v and 5v low power uart with 32-byte fifo rev. p1.0.0 preliminary 36 dc electrical characteristics for 5.0v signaling u nless otherwise noted : ta=0 o to 70 o c (-40 o to +85 o c for industrial grade package ), v cc is 5.0v +/- 10% s ymbol p arameter m in m ax u nits c ondition n otes v il input low voltage -0.5 0.8 v v ih input high voltage 2.0 6.0 v v ol output low voltage 0.4 v i ol = 6 ma v oh output high voltage 2.4 v i oh = -6 ma i il input low leakage current +/-10 ua i ih input high leakage current +/-10 ua c in input pin capacitance 5 pf i cc power supply current 1.3 ma crystal or external clock of 24mhz i sleep sleep current 100 ua uart at asleep. a2-a0 at gnd, all inputs at vcc or gnd
? ? ? ? XR16L651 2.5v, 3.3 and 5v low power uart with 32-byte fifo preliminary rev. p1.0.0 37 ac electrical characteristics for 5.0v signaling u nless otherwise noted : ta=0 o to 70 o c (-40 o to +85 o c for industrial grade package ), v cc is 5.0v +/- 10% s ymbol p arameter m in m ax u nit n otes osc crystal oscillator 24 mhz clk external clock 50 mhz t as address valid to cs# asserted 15 ns t ah cs# de-asserted to address invalid 10 ns t dly delay between cs# active cycles (16 mode) 50 ns t rd read strobe width (16 mode) 50 ns t wr write strobe width (16 mode) 50 ns t da read/write asserted to data valid 50 ns t dh read/write de-asserted to data invalid 50 ns t rws r/w# asserted to cs# asserted (68 mode) tbd ns t rwh cs# de-asserted to r/w# de-asserted (68 mode) tbd ns t csl cs# active width tbd ns t csh cs# inactive width tbd ns t 17d delay from iow# to output 50 ns t 18d delay to set interrupt from modem input 50 ns t 19d delay to reset interrupt from ior# 50 ns
XR16L651 ? ? ? ? 2.5v, 3.3v and 5v low power uart with 32-byte fifo rev. p1.0.0 preliminary 38 f igure 16. i nte l d ata b us r ead and w rite t iming a7-a0 cs# io r # d7-d0 t as t rd t ah t dly t da t dh active data active valid address a7-a0 cs# io w # d7-d0 t as t wr t ah t dly t dh 758rdwr active data active valid address read cycle timing write cycle timing active active t ds
? ? ? ? XR16L651 2.5v, 3.3 and 5v low power uart with 32-byte fifo preliminary rev. p1.0.0 39 f igure 17. m otorola d ata b us r ead and w rite t iming read cycle timing write cycle timing a4-a1 -cs d7-d0 r/-w t as t ah t rws t rwh t da t dh a4-a1 -cs d7-d0 r/-w t as t ah t rws t rwh t da t dh t csl t csh t csl t csh
XR16L651 ? ? ? ? 2.5v, 3.3v and 5v low power uart with 32-byte fifo rev. p1.0.0 preliminary 40 f igure 18. m odem i nput /o utput p ort d elay -iow -rts -dtr -cd -cts -dsr int -ior -ri t17d t18d t18d t19d t18d modem-1 active active change of state change of state active active active change of state change of state change of state active active f igure 19. t ransmit d ata i nterrupt at t rigger l evel stop bit parity bit data bits (5-8) d0 d1 d2 d3 d4 d5 d6 d7 5 data bits 6 data bits 7 data bits start bit tx data next data start bit tx interrupt at transmit trigger level baud rate clock of 16x or 8x txnofifo-1 set at below trigger level clear at above trigger level
? ? ? ? XR16L651 2.5v, 3.3 and 5v low power uart with 32-byte fifo preliminary rev. p1.0.0 41 f igure 20. r eceive d ata r eady i nterrupt at t rigger l evel stop bit parity bit data bits (5-8) d0 d1 d2 d3 d4 d5 d6 d7 start bit rx data input first byte that reaches the trigger level rx data ready interrupt at receive trigger level rxfifo1 de-asserted at below trigger level asserted at above trigger level
XR16L651 ? ? ? ? 2.5v, 3.3v and 5v low power uart with 32-byte fifo rev. p1.0.0 preliminary 42 package dimensions (48 pin tqfp - 7 x 7 x 1 mm ) 36 25 24 13 1 1 2 37 48 d d 1 d d 1 b e a a 2 a 1 a seating plane l c note: the control dimension is the millimeter column inches millimeters symbol min max min max a 0.055 0.063 1.40 1.60 a 1 0.002 0.006 0.05 0.15 a 2 0.053 0.057 1.35 1.45 b 0.007 0.011 0.17 0.27 c 0.004 0.008 0.09 0.20 d 0.346 0.362 8.80 9.20 d 1 0.272 0.280 6.90 7.10 e 0.020 bsc 0.50 bsc l 0.018 0.030 0.45 0.75 a 0 7 0 7
? ? ? ? XR16L651 2.5v, 3.3 and 5v low power uart with 32-byte fifo preliminary rev. p1.0.0 43 t able 14: explanation of data sheet revisions from to changes date - p1.0.0 initiate data sheet january 2001
? ? ? ? xrt16l651 2.5, 3.3 and 5.0v uart preliminary rev. p1.0.0 44 notice exar corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. exar corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no represen- tation that the circuits are free of patent infringement. charts and schedules contained here in are only for illustration purposes and may vary depending upon a users specific application. while the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. exar corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support sys- tem or to significantly affect its safety or effectiveness. products are not authorized for use in such applica- tions unless exar corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of exar corpo- ration is adequately protected under the circumstances. copyright 2001 exar corporation datasheet january 2001. reproduction, in part or whole, without the prior written consent of exar corporation is prohibited.
? ? ? ? XR16L651 2.5, 3.3 and 5.0v uart preliminary rev. p1.0.0 i table of contents general description ............................................................................................... 1 f eatures .............................................................................................................................. .................. 1 a pplications .............................................................................................................................. ............. 1 figure 1. block diagram ...................................................................................................... ................... 1 figure 2. intel, motorola and pc mode pin out. ............................................................................... ..... 2 ordering information ........................................................................................................................... 2 pin descriptions ........................................................................................................ 3 product description ............................................................................................... 6 functional descriptions ....................................................................................................... ...... 7 1.0 host data bus interface ................................................................................................... .................. 7 figure 3. XR16L651 intel bus interconnections ............................................................................... ..... 7 figure 4. XR16L651 motorola bus interconnections. ............................................................................ 8 figure 5. XR16L651 pc mode interconnections .................................................................................. .. 8 t able 1: pc m ode i nterface o n - chip a ddress d ecoder and i nterrupt s election . ....................... 9 figure 6. pc mode interface in an embedded application. ................................................................... 9 2.0 interrupt ................................................................................................................. ......................... 10 t able 2: i nterrupt o utput (int, int# and irqa) f unctions .......................................................... 10 3.0 crystal oscillator or external clock. ..................................................................................... ............ 11 figure 7. typical oscillator connections ..................................................................................... .......... 11 figure 8. baud rate generator ................................................................................................ ............ 11 t able 3: t ypical data rates with a 14.7456 mh z crystal or external clock ............................... 12 4.0 transmit and receive data ................................................................................................. ...... 12 5.0 automatic rts hardware flow control operation .......................................................................... 12 figure 9. auto rts and cts flow control operation ......................................................................... 13 t able 4: a uto x on /x off (s oftware ) f low c ontrol ........................................................................ 14 figure 10. infrared transmit data encoding and receive data decoding .......................................... 15 t able 5: -rxrdy pin ........................................................................................................................... 15 t able 6: -txrdy pin ........................................................................................................................... 15 figure 11. internal loop back ................................................................................................ .............. 16 t able 7: XR16L651 uart configuration registers .............................................................. 17 t able 8: uart configuration registers description. s haded bits are enabled when efr b it -4=1. ......................................................................................................................... ........................ 18 figure 12. transmitter operation in non-fifo mode ........................................................................... 20 figure 13. transmiitter operation in fifo and flow control mode ..................................................... 21 6.0 registers ................................................................................................................. ............................. 21 figure 14. receiver operation in non-fifo mode ............................................................................... 22 figure 15. receiver operation in fifo and auto rts flow control mode ......................................... 22 t able 9: i nterrupt s ource and p riority l evel ................................................................................ 24 t able 10: t ransmit and r eceive fifo t rigger l evel s election with auto rts hysteresis ........ 25 t able 11: p arity selection ................................................................................................................ 26 t able 12: s oftware f low c ontrol f unctions ................................................................................ 30 t able 13: uart reset conditions .............................................................................................. 31 a bsolute m aximum r atings .......................................................................................................... 32 electrical characteristics (preliminary) .................................................. 32 dc e lectrical c haracteristics for 2.5v s ignaling ........................................................................ 32 ac e lectrical c haracteristics for 2.5v s ignalling ....................................................................... 33 dc e lectrical c haracteristics for 3.3v s ignaling ........................................................................ 34 ac e lectrical c haracteristics for 3.3v s ignaling ......................................................................... 35 dc e lectrical c haracteristics for 5.0v s ignaling ........................................................................ 36 ac e lectrical c haracteristics for 5.0v s ignaling ......................................................................... 37 figure 16. intel data bus read and write timing .............................................................................. 38 figure 17. motorola data bus read and write timing ........................................................................ 39
XR16L651 ? ? ? ? 2.5, 3.3 and 5.0v uart rev. p1.0.0 preliminary ii figure 18. modem input/output port delay ..................................................................................... ..... 40 figure 19. transmit data interrupt at trigger level .......................................................................... ... 40 figure 20. receive data ready interrupt at trigger level ................................................................... 4 1 package dimensions (48 pin tqfp - 7 x 7 x 1 mm ) .............................................. 42 t able 14: explanation of data sheet revisions .................................................................. 43 table of contents ............................................................................................................. .............. i

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